`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Westlake University
// Engineer: shenziyang@westlake.edu.cn 
// 
// Create Date: 2021/11/22 15:33:29
// Design Name: HW2
// Module Name: tb_BCD_dec_adder2bit
// Project Name: hw2
// Target Devices: VCU118
// Tool Versions: vivado 2020.1
// Description: testbench for homework2 BCD_dec_adder2bit
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module tb_BCD_dec_adder2bit();
    reg cin;
    reg clk;
    reg ena;
    reg rst_n;
    wire cout;
    wire [1:0] D;
    wire [1:0] C;
    wire [1:0] B;
    wire [1:0] A;

    always begin                    //clock generation
        #5 clk = 1; #5 clk = 0;
    end
    initial begin                   //initialization
        ena = 1;
        cin = 0;
        rst_n = 1;
        #10 rst_n = 0;
        #110 $finish;
    end

BCD_dec_adder2bit inst_BCD_dec_adder2bit(cin, clk, ena, rst_n, cout, D, C, B, A);
endmodule
